1. Field of the Invention
The present invention relates to a method for manufacturing a semiconductor device, and more particularly, the present invention relates to a method for manufacturing a semiconductor device, in which, in order to prevent a semiconductor substrate from being damaged when implementing a metal wiring contact process for forming a metal wiring of a peripheral circuit part, a capping nitride film positioned above a word line of the peripheral circuit part is first etched and then subsequent processes are performed, thereby minimizing the extent to which the semiconductor substrate is damaged during the metal wiring contact process.
2. Description of the Related Art
A recent trend for the high integration of a semiconductor device is largely influenced by a development of a micro-pattern forming technique. In order to accomplish the high integration of a semiconductor device, it is regarded as being indispensable to make a photoresist film pattern which is widely used as a mask in an etching process or an ion-implanting process so that the photoresist film pattern has a micro dimension.
A resolution R of a photoresist film pattern is proportional to a wavelength of light emitted from a light source of a stepper and a process parameter k and is inversely proportional to a lens diameter NA (numerical aperture). The resolution R can be expressed by the following equation: EQU R=k*.lambda./NA,
where R=resolution, .lambda.=wavelength of light source, NA=numerical aperture
Here, in order to improve the resolution of the stepper, the wavelength is generally reduced. For example, steppers using light sources such as a G-line and an I-line respectively having wavelengths of 436 nm and 365 nm have limitations of that they have light resolutions capable of forming patterns with dimensions of about 0.7 .mu.m and 0.5 .mu.m, respectively. In order to form a micro pattern which is no greater than 0.5 .mu.m, an exposure system which employs as its light source a deep ultra violet (DUV) having a small wavelength, that is, a KrF laser having a wavelength of 248 nm or an ArF laser having a wavelength of 193 nm, is used.
Also, as means for improving a resolution by virtue of modifying processes, a method for using a phase shift mask instead of a photo mask, a contrast enhancement layer (CEL) method in which a separate thin film capable of enhancing an image contrast is formed on a wafer, a tri layer resist (TLR) method in which an intermediate layer such as a spin-on-glass (SOG) film is intervened between two photoresist films, a sililation method in which silicon is selectively injected onto a photoresist film, etc. may be used.
In addition, as a semiconductor device is gradually highly integrated, a contact hole for connecting upper and lower conductor wiring is decreased in its size, a spacing between the contact hole and an adjacent wiring is decreased, and an aspect ratio which is a ratio between a diameter and a depth of the contact hole is increased. Accordingly, in a highly integrated semiconductor device having multi-layered conductor wirings, in order to form a contact, it is required that masks be precisely and strictly aligned one with another during manufacturing processes of the semiconductor device, whereby a process margin is diminished.
In order to maintain a proper spacing between contact holes, masks are formed considering a misalignment tolerance when aligning the masks, a lens distortion when implementing an exposing process, a critical dimension variation when preparing masks and implementing photolithographic processes, a registration between masks, and so on.
Further, in order to overcome limitations in performing a lithographic process for forming a contact hole, a self-aligning contact (SAC) technology which forms a contact hole by a self-aligning method is disclosed in the art.
While the SAC method may use a polysilicon, a nitride film or an oxidized nitride film in a preferred fashion, the SAC method uses a nitride film.
While not shown in the drawings, a method for manufacturing a semiconductor device using the self-aligning contact technology, according to the conventional art, will be described hereinafter.
First, a predefined lower structure, for example, a MOS field effect transistor (MOSFET) having a device isolating insulation film and a gate insulation film, a gate electrode which is overlapped with a mask oxide film pattern, source/drain regions, etc. is formed on a semiconductor substrate. Then, an etch barrier and an interlayer insulation film made of an oxide are sequentially formed on an entire surface of the resultant structure.
Then, after forming a photoresist film pattern for revealing the interlayer insulation film positioned on a portion which is predefined as a contact such as for a storage electrode and a bit line in the semiconductor substrate, the etch barrier is revealed by dry etching the interlayer insulation film which is revealed by the photoresist film pattern, and a contact hole is formed by etching the etch barrier again.
In the above description, if a polysilicon is used as the etch barrier, the etch barrier can be forwardly formed or a polysilicon layer pad can be formed only at a region where the contact hole is to be formed. In the polysilicon SAC method, since the polysilicon having an etching mechanism other than as in an oxide film, is used as the etch barrier, a high etch selection ratio can be obtained, but in a vapor deposition method over an entire surface, insulation reliability between contact holes is deteriorated. Also, in a method of forming a pad, in case that a misalignment is generated between a contact pad and a silicon substrate, the silicon substrate can be damaged. Moreover, in order to prevent the silicon substrate from being damaged, a method for enlarging a contact pad using a spacer or a polymer is disclosed in the art. However, with this method, a design rule of no greater than 0.18 .mu.m cannot be realized.
To cope with this problem, another SAC method in which a nitride film is used as an etch barrier is disclosed in the art.
As a result, in the method for manufacturing a semiconductor device according to the conventional art, constructed as mentioned above, as a semiconductor device is gradually highly integrated, because a topology is increased between the cell part and the peripheral circuit part, the nitride film above the gate electrode which is formed on the peripheral circuit part having a low topology may not be etched when implementing the etching process for forming the metal wiring contact, and according to this, the metal wiring contact may not be fully opened. In addition, a junction region of the semiconductor substrate may be damaged while the nitride film is completely etched, and according to this, a leakage current can be induced thereby degrading a process yield and reliability in a device operation.